RK3588 Carrier Board Hardware Design Review Checklist: Schematic to PCB

A pre-layout hardware review for an RK3588 carrier board aims to move "will it come up" risk upstream and leave debug hooks on the first spin. It covers the power tree and sequencing, reset and boot-mode configuration, high-speed differential routing, clocks and GPIO muxing, ESD protection, and testability. Leaving enough debug hooks on the first board shortens bring-up time considerably.

How Does This Differ from a Software Bring-Up Checklist?

There is a companion article, "RK3588/RK3576 New Carrier Board BSP Bring-Up Checklist," written from the software side of getting a system to run. This article is the pre-layout hardware design review that happens before the schematic and PCB are frozen. The time points and goals differ: the hardware review answers "is the board designed correctly," while software bring-up answers "how do we debug the board once it is back." Run the hardware review as a distinct gate and keep records, so design defects are not discovered only during bring-up.

What Should the Schematic Review Cover?

The table lists the high-frequency review items; add or remove per project.

How Do You Review MIPI, USB3, and PCIe High-Speed Routing?

• Differential impedance: control traces to the target impedance in the platform design guide; discontinuity causes reflections and eye-diagram degradation (specific values belong in the official design guide).
• Length matching: match within a pair first, then control inter-pair and inter-group skew to the interface requirement so timing margin is not consumed.
• Reference plane: keep a solid ground reference, avoid plane splits, and watch return-path continuity at layer transitions.
• Vias and layer changes: limit via count and layer changes, and place ground return vias near each transition.

High-speed problems are often not single-point errors but the accumulation of "a little off everywhere." Treat each high-speed interface as its own check item and go through the design guide line by line rather than skimming.

What Are Easy-to-Miss Points in Clocks, GPIO Muxing, and Mechanicals?

• Clocks and reference crystals: verify crystal accuracy, load capacitance, and layout; reference clock quality directly affects interface stability and audio peripherals.
• GPIO muxing and pull-ups/downs: confirm muxed functions do not conflict with required peripherals, and that key pin levels during reset are as expected.
• Mounting holes and height limits: check hole positions, keep-out zones, and enclosure height limits; heat sinks and shields need enough mechanical clearance.
• Shields and grounding: reserve shield and ground-clip locations for RF and high-speed parts to avoid later wire fixes.

How Do You Reserve Testability and Production Tooling?

Poor testability makes production testing expensive. On the first spin, reserve a debug UART output, test points on key rails and signals, flashing and fixture interfaces, and a fixture-alignment structure for automated test. Consider probe accessibility for test points so heat sinks and large parts do not block them. These reservations cost little but noticeably cut production test time and fixture complexity.

Why Reserve Generous Debug Hooks on the First Spin?

First-spin hardware is never perfect in one pass. The value of debug hooks is separating "finding" a problem from "fixing" it: with a debug UART, test points, and spare interfaces, an issue can be located and verified on the prototype without a board respin. In practice, projects that reserve ample debug hooks bring up noticeably faster; conversely, a board without test points and spare paths can push even a small issue to the next respin. Make debug reservation a fixed review item, not an option.

FAQ

• Q1: When should the hardware review happen?Once after the schematic is complete and once before the PCB is frozen, focused on power, boot config, high-speed routing, and testability; keep records for traceability.
• Q2: Does this checklist overlap with a BSP bring-up checklist?No. The former targets design correctness before layout; the latter targets software bring-up after the board returns. They have different time points and can reference each other but do not replace each other.
• Q3: Which debug hooks should the first spin reserve?At least a debug UART, test points on key rails and signals, and flashing and fixture interfaces, with probe accessibility and enclosure space in mind.
• Q4: Which part of high-speed routing is hardest?Usually reference-plane integrity and impedance consistency. Single-point specs are easy to hit; keeping every segment on the path within tolerance is the hard part, so review each interface against the design guide.